


--Enderecos
--	FFD7 - CONFIG_SERIAL (end_base)
--	FFD8 - DATA
--	FFD9 - DIVISOR


library ieee;
use ieee.std_logic_1164.all;

entity serial is 
 
 generic( valor_rst : std_logic := '1';  -- rst barrado/nao-barrado
			  def_configserial : std_logic_vector (15 downto 0) := x"0000";  -- default dos rsts
			  def_data : std_logic_vector (15 downto 0) := x"0000";
			  def_divisor : std_logic_vector (15 downto 0) := x"0000"); 
			  
  port(ADR : in std_logic_vector(15 downto 0);
		 W, EN, ck, rst : in std_logic;
		 INT : out std_logic;
		 DADO : inout std_logic_vector(15 downto 0)
		 ) ; 
end serial;



architecture descricao of serial is 


signal  CONFIG_SERIAL, DATA, DIVISOR, dado_interno : std_logic_vector(15 downto 0);


	begin

		dado_interno <=   CONFIG_SERIAL  when ADR = x"FFD7" else -- DADO TRISTATE
					         DATA			 when ADR = x"FFD8" else
								DIVISOR		 when ADR = x"FFD9" else
				( others => 'Z' );
					
process(ck,rst)

			begin
			
				if rst = valor_rst then -- condicao de reset
					CONFIG_SERIAL <= def_configserial;
					DATA          <= def_data;
					DIVISOR       <= def_data;
				
				elsif rising_edge(ck) then
					
				
				end if;
end process;
						
  
end descricao;